Generally, semiconductor memory devices are divided into a volatile memory devices and a non-volatile memory devices. Example volatile memory device include random access memory (RAM), dynamic RAM (DRAM), and static RAM (SRAM). Volatile memory devices are characterized in that data stored in volatile memory devices is erased when power is removed from the volatile memory device.
As opposed to volatile memory devices, non-volatile memory devices, such as read only memory (ROM) retain their contents when power is removed from the non-volatile memory devices.
Currently, non-volatile memory devices are divided into floating gate based memory and metal insulator semiconductor (MIS) based memory. Floating gate based memory devices operate using a potential well. Typical floating gate based memory devices include an erasable programmable read only memory (EPROM) tunnel oxide (ETOX) structure that is applied as a flash electrically erasable programmable read only memory (EEPROM).
MIS based memory is characterized in that such devices include two or more kinds of dielectric layers that are stacked to form a double layer or a triple layer device. MIS based memory devices utilize a trap that exists in an interface between the dielectric bulk and the dielectric layer, and between the dielectric layer and the semiconductor. Example MIS based memory devices include metal oxide-nitride-oxide semiconductor (MONOS) and silicon oxide-nitride-oxide semiconductor (SONOS) structures that are applied as electrically erasable programmable read only memory (EEPROM).
A conventional flash memory having the oxide-nitride-oxide (ONO) structure is illustrated in FIG. 1. As shown in FIG. 1, a tunneling oxide layer 2 having a predetermined width and a thickness of about 100 Å is formed on a semiconductor substrate 1. A floating gate 3 formed of polycrystalline silicon and having a thickness of about 2500 Å is formed thereon. A dielectric layer 4 of an ONO structure is formed on the floating gate 3.
A control gate 5 formed of polycrystalline silicon and having a thickness of about 2500 Å is formed on the dielectric layer 4. A side wall 6 is formed on both side wall of the control gate 5, the dielectric layer 4, the floating gate 3, and the tunneling oxide layer 2.
A source 7 and a drain 8 are formed in the semiconductor substrate 1 located outside of the control gate 5, the dielectric layer 4, the floating gate 3 and the tunneling oxide layer 2.
Technical development for reducing the size of the flash memory as described above is currently being undertaken, however, there is still a limitation on reducing the device size. For example, mass production of an ultra fine silicon device needing an ultra fine pattern cannot realized because there is no settled technique using a new process for forming patterns, such as an exposure method using an electron beam or an X-ray to fabricate a nano-sized channel of the device.